Highly selective spacer etch process with reduced sidewall spacer slimming

ABSTRACT

A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure. The spacer etch process sequence may include oxidizing an exposed surface of the spacer material to form a spacer oxidation layer, performing a first etching process to anisotropically remove the spacer oxidation layer from the spacer material at the substrate region on the substrate and the spacer material at the capping region of the gate structure, and performing a second etching process to selectively remove the spacer material from the substrate region on the substrate and the capping region of the gate structure to leave behind the spacer sidewall on the sidewall of the gate structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of pending U.S. patentapplication Ser. No. 13/336,388 filed Dec. 23, 2011, and entitled,“HIGHLY SELECTIVE SPACER ETCH PROCESS WITH REDUCED SIDEWALL SPACERSLIMMING,” which has now been allowed as a patent, the entire contentsof which is incorporated herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a method of preparing a sidewall spacer for atransistor gate on a substrate.

2. Description of Related Art

In semiconductor manufacturing and during the fabrication of atransistor gate, a spacer material is conformally applied to thetransistor gate, and then partially removed to form a sidewall spacer ona sidewall of the transistor gate. During the partial removal of thespacer material from the transistor gate top and the substrate, thesuccess of a spacer etch process is determined by measuring, among otherthings, the following performance metrics: (a) the size of the sidewallspacer footing, (b) the depth of the substrate recess, (c) the amount ofsidewall spacer critical dimension (CD) slimming, and (d) the depth ofthe spacer top recess. Conventional spacer etch processes produceunacceptable results in at least one of these performance metrics.

SUMMARY OF THE INVENTION

Embodiments of the invention relate to a method of preparing a sidewallspacer and, in particular, to a method of preparing a sidewall spacerfor a transistor gate on a substrate.

According to one embodiment, a method for performing a spacer etchprocess is described. The method includes conformally applying a spacermaterial over a gate structure on a substrate, and performing a spaceretch process sequence to partially remove the spacer material from acapping region of the gate structure and a substrate region on thesubstrate adjacent a base of the gate structure, while retaining aspacer sidewall positioned along a sidewall of the gate structure. Thespacer etch process sequence may include oxidizing an exposed surface ofthe spacer material to form a spacer oxidation layer, performing a firstetching process to anisotropically remove the spacer oxidation layerfrom the spacer material at the substrate region on the substrate andthe spacer material at the capping region of the gate structure, andperforming a second etching process to selectively remove the spacermaterial from substrate region on the substrate and the capping regionof the gate structure to leave behind the spacer sidewall on thesidewall of the gate structure.

According to another embodiment, a method for performing a spacer etchprocess is described. The method includes receiving a substrate having aspacer material conformally applied over a gate structure on saidsubstrate, and performing a spacer etch process sequence to partiallyremove the spacer material from a capping region of the gate structureand a substrate region on the substrate adjacent a base of the gatestructure, while retaining a spacer sidewall positioned along a sidewallof the gate structure. The spacer etch process sequence may includeoxidizing an exposed surface of the spacer material to form a spaceroxidation layer, performing a first etching process to anisotropicallyremove the spacer oxidation layer from the spacer material at thesubstrate region on the substrate and the spacer material at the cappingregion of the gate structure, and performing a second etching process toselectively remove the spacer material from the substrate region on thesubstrate and the capping region of the gate structure to leave behindthe spacer sidewall on the sidewall of the gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A through 1C illustrate a schematic representation of thepreparation of a sidewall spacer for a gate structure on a substrate;

FIGS. 2A through 2D illustrate a schematic representation of a methodfor performing a spacer etch process according to an embodiment;

FIG. 3 provides a flow chart illustrating a method for performing aspacer etch process according to an embodiment;

FIG. 4 provides a flow chart illustrating a method for performing aspacer etch process according to additional embodiments;

FIG. 5 shows a schematic representation of a plasma processing systemaccording to an embodiment;

FIG. 6 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 7 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 8 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 9 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 10 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 11 shows a schematic representation of a plasma processing systemaccording to another embodiment;

FIG. 12 depicts a cross-sectional view of a plasma source in accordancewith one embodiment;

FIGS. 13A and 13B depict a cross-sectional view and bottom view of aplasma source in accordance with another embodiment; and

FIG. 14 depicts a cross-sectional view of a plasma source in accordancewith yet another embodiment.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

In the following description, for purposes of explanation and notlimitation, specific details are set forth, such as a particulargeometry of a processing system, descriptions of various components andprocesses used therein. However, it should be understood that theinvention may be practiced in other embodiments that depart from thesespecific details.

Similarly, for purposes of explanation, specific numbers, materials, andconfigurations are set forth in order to provide a thoroughunderstanding of the invention. Nevertheless, the invention may bepracticed without specific details. Furthermore, it is understood thatthe various embodiments shown in the figures are illustrativerepresentations and are not necessarily drawn to scale.

Various operations will be described as multiple discrete operations inturn, in a manner that is most helpful in understanding the invention.However, the order of description should not be construed as to implythat these operations are necessarily order dependent. In particular,these operations need not be performed in the order of presentation.Operations described may be performed in a different order than thedescribed embodiment. Various additional operations may be performedand/or described operations may be omitted in additional embodiments.

“Substrate” as used herein generically refers to the object beingprocessed in accordance with the invention. The substrate may includeany material portion or structure of a device, particularly asemiconductor or other electronics device, and may, for example, be abase substrate structure, such as a semiconductor wafer or a layer on oroverlying a base substrate structure such as a thin film. Thus,substrate is not intended to be limited to any particular basestructure, underlying layer or overlying layer, patterned orun-patterned, but rather, is contemplated to include any such layer orbase structure, and any combination of layers and/or base structures.The description below may reference particular types of substrates, butthis is for illustrative purposes only and not limitation.

As noted above in semiconductor manufacturing, when fabricating atransistor gate, a spacer material is conformally applied to thetransistor gate, and then partially removed to form a sidewall spacer ona sidewall of the transistor gate. For example, FIG. 1A provides apictorial illustration of a gate structure 100 formed on substrate 110,wherein the gate structure 100 includes a gate dielectric 120, a gateelectrode 130, and a gate capping layer 140. Therein, the gatedielectric 120 may be characterized by an initial gate dielectricthickness 121 (e.g., about 10-40 nm (nanometers)), and the gateelectrode 130 may be characterized by an initial gate electrodethickness 131 (e.g., about 30-100 nm). Further, the gate capping layer140 may be characterized by an initial gate capping layer thickness 141(e.g., about 10-20 nm).

A spacer material layer 150, characterized by an initial spacer materiallayer critical dimension (CD) 151, is subsequently formed over the gatestructure 100. The spacer material layer 150 may be applied via a vapordeposition process to conform to the topography of the gate structure100, as illustrated in FIG. 1A. For example, the spacer material layer150 may be deposited using a chemical vapor deposition (CVD) process, aplasma-enhanced CVD (PECVD) process, an atomic layer deposition (ALD)process, a plasma-enhanced ALD (PEALD) process, a physical vapordeposition (PVD) process, a sputtering process, etc. The initial spacermaterial layer CD 151 may range from about 2 nm (nanometers) to about 20nm, or preferably from about 5 nm to about 15 nm, or more preferablyfrom about 8 nm to about 12 nm (e.g., about 9-10 nm).

During the partial removal of the spacer material layer 150 from thetransistor gate 100 and the substrate 110 to create a sidewall spacer(150A, 150B), the spacer etch process is evaluated by measuring, amongother things, the following performance metrics: (a) the amount of CDreduction or slimming of the spacer material layer 150 along thesidewall of the gate structure 100, (b) the existence and/or size of asidewall spacer footing, (c) the amount of substrate recess exhibited inan exposed surface of the substrate, (d) the amount of spacer recessexhibited in the spacer material layer 150 proximate the top of the gatestructure 100, and (e) the amount of capping material consumed from thetop surface of the gate capping layer 140.

As illustrated in FIG. 1B, conventional spacer etch processes produceunacceptable results in at least one of these performance metrics. Forexample, following a conventional spacer etch process, a gate structure101 is produced having a sidewall spacer 150A characterized by a finalspacer material layer CD 151A. The difference between the final spacermaterial CD 151A and the initial spacer material CD 151 is a measure ofthe amount of CD reduction or slimming of the spacer material layer 150.The amount of CD reduction or slimming can be excessive, and oftentimescan exceed 20%, 30%, and even 50% the initial spacer material CD 151.

Additionally, for example, gate structure 101 may exhibit a sidewallspacer footing 152A. Furthermore, for example, gate structure 101 mayexhibit any one of the following: (i) a substrate recess formed in anexposed surface of substrate 110 and characterized by a substrate recessdepth 112A that may exceed 1 nm, 2 nm, and even 5 nm; (ii) a spacerrecess in the spacer material layer 150 proximate the top of the gatestructure 101 and characterized by a spacer recess depth 153A that mayexceed 1 nm, 2 nm, and even 5 nm; and (iii) amount of capping materialconsumed from the top surface of the gate capping layer 140A andcharacterized by the difference between a final gate capping layerthickness 141A and the initial gate capping layer thickness 141 that mayexceed 5 nm.

As illustrated in FIG. 1C and further described below, a spacer etchprocess is presented that produces acceptable results in at least one ofthese performance metrics. For example, following the spacer etchprocess, a gate structure 102 is produced having a sidewall spacer 150Bcharacterized by a final spacer material layer CD 151B. The differencebetween the final spacer material CD 151B and the initial spacermaterial CD 151 is a measure of the amount of CD reduction or slimmingof the spacer material layer 150. The amount of CD reduction or slimmingmay be reduced to less than 2 nm, and desirably less than 1 nm.Alternatively, the amount of CD reduction or slimming may be reduced toless than 20%, and desirably less than 10% of the initial spacermaterial CD 151.

Additionally, for example, gate structure 102 may exhibit a reduced orsubstantially no sidewall spacer footing 152B. Furthermore, for example,gate structure 102 may exhibit any one of the following: (i) a reducedsubstrate recess formed in an exposed surface of substrate 110 andcharacterized by a substrate recess depth 112B that may be less than 3nm, 2 nm, and even 1 nm; (ii) a spacer recess in the spacer materiallayer 150 proximate the top of the gate structure 102 and characterizedby a spacer recess depth 153B that may be less than 5 nm, 2 nm, and even1 nm; and (iii) amount of capping material consumed from the top surfaceof the gate capping layer 140 that produces a final gate capping layer140B characterized by the difference between a final gate capping layerthickness 141B and the initial gate capping layer thickness 141 that maybe less than 5 nm.

Therefore, according to various embodiments, a method for performing aspacer etch process is described. The method is pictorially illustratedin FIGS. 2A through 2D, and presented by way of a flow chart 300 in FIG.3. As presented in FIG. 3, the flow chart 300 begins in 310 withconformally applying a spacer material 250 over a gate structure 200 ona substrate 210 (see FIG. 2A). The spacer material 250 may include anitride, such as silicon nitride (Si_(x)N_(y)). Additionally, the spacermaterial 250 may include a carbide, such as silicon carbide(Si_(x)C_(y)). Furthermore, the spacer material 250 may include acarbonitride, such as silicon carbonitride (Si_(x)C_(y)N_(z)). Furtheryet, the spacer material 250, conformally applied over the gatestructure 200, may have a thickness less than or equal to about 20 nm,or less than or equal to about 10 nm.

The gate structure 200 comprises a patterned film stack of one or morelayers 230 that may include, among other things, a gate capping layer, agate electrode layer, a gate dielectric layer, a gate interfacial layer,etc. The gate capping layer may include an oxide, such as SiO₂.

The gate electrode layer may include a layer of polycrystalline silicon(polysilicon, or poly-Si) and/or a metal-containing layer. Themetal-containing layer may include a metal, a metal alloy, a metalnitride, or a metal oxide, and may contain, for example, titanium,titanium aluminum alloy, tantalum, tantalum aluminum alloy, titaniumnitride, titanium silicon nitride, titanium aluminum nitride, tantalumnitride, tantalum silicon nitride, hafnium nitride, hafnium siliconnitride, aluminum nitride, or aluminum oxide. The metal-containing layermay replace or be integrated with a traditional poly-Si gate electrodelayer.

The gate dielectric may include SiO₂, or a high-k (high dielectricconstant) layer, and may, for example, include a lanthanum-containinglayer, such as lanthanum oxide (LaO), or a hafnium containing layer,such as a hafnium oxide layer (e.g., HfO_(x), HfO₂), a hafnium silicatelayer (e.g., HfSiO), or a nitrided hafnium silicate (e.g., HfSiO(N)).Additionally, for example, the high-k layer may incorporate metallicsilicates or oxides (e.g., Ta₂O₅ (k˜26), TiO₂ (k˜80), ZrO₂ (k˜25), Al₂O₃(k˜9), HfSiO, HfO₂ (k˜25)). Furthermore, for example, the high-k layermay include mixed rare earth oxides, mixed rare earth aluminates, mixedrare earth nitrides, mixed rare earth aluminum nitrides, mixed rareearth oxynitrides, or mixed rare earth aluminum oxynitrides. The gateinterfacial layer may include a thin layer of silicon dioxide (SiO₂)disposed between the high-k layer and the substrate 210.

The substrate 210 may include a bulk silicon substrate, a single crystalsilicon (doped or un-doped) substrate, a semiconductor-on-insulator(SOI) substrate, or any other semiconductor substrate containing, forexample, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, as well as otherIII/V or II/VI compound semiconductors, or any combination thereof(Groups II, III, V, VI refer to the classical or old IUPAC notation inthe Periodic Table of Elements; according to the revised or new IUPACnotation, these Groups would refer to Groups 2, 13, 15, 16,respectively). The substrate can be of any size, for example, a 200 mm(millimeter) substrate, a 300 mm substrate, a 450 mm substrate, or aneven larger substrate.

In 320, a spacer etch process sequence is performed to partially removethe spacer material 250 from a capping region 201 of the gate structure200 and a substrate region 202 on substrate 210 adjacent a base 232 ofthe gate structure 200, while retaining a spacer sidewall 280 positionedalong a sidewall 235 of the gate structure 200. As illustrated in FIG.4, a method for performing a spacer etch process sequence is described.

The method includes a flow chart 400 beginning in 410 with oxidizing anexposed surface 252 of the spacer material 250 to form a spaceroxidation layer 260 (see FIG. 2B). The spacer oxidation layer 260 may beformed by exposing the spacer material 250 to an oxygen-containingenvironment. The oxygen-containing environment may include monatomicoxygen (O), diatomic oxygen (O₂), triatomic oxygen (ozone, O₃), anoxygen-containing molecule, ionized oxygen, metastable oxygen, or anyexcited state of oxygen, or any combination of two or more thereof. Forexample, the oxygen-containing environment may include anoxygen-containing plasma. Additionally, for example, theoxygen-containing environment may contain O, O₂, O₃, CO, CO₂, NO, N₂O,or NO₂, or any combination of two or more thereof. The oxygen-containingenvironment may be generated in-situ or ex-situ relative to substrate210.

In 420, a first etching process is performed to anisotropically removethe spacer oxidation layer 260 from the spacer material 250 at thesubstrate region 202 on substrate 210 and the spacer material 250 at thecapping region 201 of the gate structure 200 to leave behind a sidewallspacer oxidation layer 265 (see FIG. 2C).

The first etching process may include forming plasma from a firstetching process composition that contains a halomethane gas. Thehalomethane gas may include a mono-substituted halomethane (e.g., CH₃F),a di-substituted halomethane (e.g., CH₂F₂), a tri-substitutedhalomethane (e.g., CHF₃), or a tetra-substituted halomethane (e.g., CE).

Additionally, for example, the first etching process composition mayinclude a hydrocarbon (i.e., C_(x)H_(y), where x and y are equal tounity or greater). Alternatively, for example, the first etching processcomposition may include a fluorocarbon (i.e., C_(x)F_(y), where x and yare equal to unity or greater). Alternatively yet, for example, thefirst etching process composition may include an additive gas having thechemical formula C_(x)H_(y)R_(z), where R is a halogen element, x and yare equal to unity or greater, and z is equal to zero or greater.

The first etching process composition may include a noble gas. The firstetching process composition may include an oxygen-containing gas, ahydrogen-containing gas, a nitrogen-containing gas, or acarbon-containing gas, or any combination of two or more thereof. Forexample, the first etching process composition may include H₂, O₂, N₂,CO, CO₂, NH₃, NO, N₂O, or NO₂, or any combination of two or morethereof. The first etching process composition may further include afluorine-containing gas, a chlorine-containing gas, a bromine-containinggas, or a halide gas. For example, the first etching process compositionmay further include HBr, F₂, Cl₂, Br₂, BCl₃, NF₃, or SF₆.

To form the plasma in the first etching process, constituents of theetching process composition should be selected that exist in a gaseousand/or vapor phase either alone or in combination with a carrier gas(e.g., a noble gas element or nitrogen) at atmospheric and/or vacuumpressures.

In one embodiment, the first etching process composition may includeCH₃F and Ar. In another embodiment, the first etching processcomposition may include CF₄ and Ar.

As described above, substrate 210 is exposed to the plasma toanisotropically remove the spacer oxidation layer 260 from the spacermaterial 250. The first etching process may include preparation of afirst etch process recipe. The first etch process recipe may include oneor more process conditions defined by one or more process parameters.The one or more process conditions may be established by setting one ormore process parameters, such as: setting a flow rate of the processcomposition; setting a pressure in the plasma processing system; settinga first radio frequency (RF) power level for a first RF signal appliedto a lower electrode within a substrate holder for supporting andelectrically biasing the substrate; setting a second RF (or microwave)power level for a second RF signal applied to a source antenna orelectrode opposing the lower electrode above the substrate; setting atemperature condition for the plasma processing system; setting atemperature condition for the substrate or substrate holder; setting anetch time; and/or setting an over-etch time. During the first etchingprocess, any one of the process parameters may be varied.

In one embodiment, the first etching process may comprise a processparameter space that includes: a chamber pressure ranging up to about1000 mtorr (millitorr) (e.g., up to about 200 mtorr, or ranging fromabout 30 to about 100 mtorr, or less than 50 mTorr, or less than 40mTorr, or less than 30 mTorr, or less than 25 mTorr,), a process gas(e.g., CF₄) flow rate ranging up to about 2000 sccm (standard cubiccentimeters per minute) (e.g., up to about 1000 sccm, or about 1 sccm toabout 200 sccm), an optional additive gas flow rate ranging up to about2000 sccm (e.g., up to about 1000 sccm, or up to about 100 sccm, or upto about 10 sccm), an optional noble gas (e.g., He or Ar) flow rateranging up to about 2000 sccm (e.g., up to about 2000 sccm, or up toabout 1000 sccm), a SWP (surface wave plasma) source (e.g., element 1130in FIG. 11) power ranging up to about 3000 W (watts) (e.g., up to about2500 W, or ranging from about 1500 W to about 2500 W), and a lowerelectrode (e.g., element 522 in FIG. 11) RF power level for electricallybiasing the substrate ranging up to about 1000 W (e.g., up to about 500W, or up to about 300 W, or up to 250 W). Also, the SWP source canoperate at a microwave frequency, e.g., 2.48 GHz. In addition, the lowerelectrode bias frequency can range from about 0.1 MHz to about 100 MHz,e.g., about 2 MHz or 13.56 MHz.

In 430, a second etching process is performed to selectively remove thespacer material 250 from the substrate region 202 on substrate 210 andthe capping region 201 of the gate structure 200 to leave behind thespacer sidewall 280, which may include sidewall spacer material 255 anda reduced sidewall spacer oxidation layer 270, on the sidewall 235 ofthe gate structure 200 (see FIG. 2D).

The second etching process may include forming plasma from a secondetching process composition that contains a halomethane gas. Thehalomethane gas may include a mono-substituted halomethane (e.g., CH₃F),a di-substituted halomethane (e.g., CH₂F₂), a tri-substitutedhalomethane (e.g., CHF₃), or a tetra-substituted halomethane (e.g.,CF₄).

Additionally, for example, the second etching process composition mayinclude a hydrocarbon (i.e., C_(x)H_(y), where x and y are equal tounity or greater). Alternatively, for example, the second etchingprocess composition may include a fluorocarbon (i.e., C_(x)F_(y), wherex and y are equal to unity or greater). Alternatively yet, for example,the second etching process composition may include an additive gashaving the chemical formula C_(x)H_(y)R_(z), where R is a halogenelement, x and y are equal to unity or greater, and z is equal to zeroor greater.

The second etching process composition may include a noble gas. Thesecond etching process composition may include an oxygen-containing gas,a hydrogen-containing gas, a nitrogen-containing gas, or acarbon-containing gas, or any combination of two or more thereof. Forexample, the second etching process composition may include H₂, O₂, N₂,CO, CO₂, NH₃, NO, N₂O, or NO₂, or any combination of two or morethereof. The second etching process composition may further include afluorine-containing gas, a chlorine-containing gas, a bromine-containinggas, or a halide gas. For example, the second etching processcomposition may further include HBr, F₂, Cl₂, Br₂, BCl₃, NF₃, or SF₆.

To form the plasma in the second etching process, constituents of theetching process composition should be selected that exist in a gaseousand/or vapor phase either alone or in combination with a carrier gas(e.g., a noble gas element or nitrogen) at atmospheric and/or vacuumpressures.

In one embodiment, the second etching process composition may includeCH₃F, O₂, and Ar.

As described above, substrate 210 is exposed to the plasma toselectively remove the spacer material 250 from the substrate region 202on substrate 210 and the capping region 201 of the gate structure 200.The second etching process may include preparation of a second etchprocess recipe. The second etch process recipe may include one or moreprocess conditions defined by one or more process parameters. The one ormore process conditions may be established by setting one or moreprocess parameters, such as: setting a flow rate of the processcomposition; setting a pressure in the plasma processing system; settinga first radio frequency (RF) power level for a first RF signal appliedto a lower electrode within a substrate holder for supporting andelectrically biasing the substrate; setting a second RF (or microwave)power level for a second RF signal applied to a source antenna orelectrode opposing the lower electrode above the substrate; setting atemperature condition for the plasma processing system; setting atemperature condition for the substrate or substrate holder; setting anetch time; and/or setting an over-etch time. During the first etchingprocess, any one of the process parameters may be varied.

In one embodiment, the second etching process may comprise a processparameter space that includes: a chamber pressure ranging up to about1000 mtorr (millitorr) (e.g., up to about 200 mtorr, or ranging fromabout 30 to about 150 mtorr, or about 50 mTorr to about 120 mTorr), aprocess gas (e.g., CH₃F) flow rate ranging up to about 2000 sccm(standard cubic centimeters per minute) (e.g., up to about 1000 sccm, orabout 1 sccm to about 200 sccm, or about 1 sccm to about 100 sccm, orabout 1 sccm to about 50 sccm), an optional additive gas (e.g., O₂) flowrate ranging up to about 2000 sccm (e.g., up to about 1000 sccm, or upto about 100 sccm, or up to about 20 sccm), an optional noble gas (e.g.,He or Ar) flow rate ranging up to about 2000 sccm (e.g., up to about2000 sccm, or up to about 1000 sccm), a SWP (surface wave plasma) source(e.g., element 1130 in FIG. 11) power ranging up to about 3000 W (watts)(e.g., up to about 2500 W, or ranging from about 1500 W to about 2500W), and a lower electrode (e.g., element 522 in FIG. 11) RF power levelfor electrically biasing the substrate ranging up to about 1000 W (e.g.,up to about 500 W, or up to about 300 W, or up to 250 W). Also, the SWPsource can operate at a microwave frequency, e.g., 2.48 GHz. Inaddition, the lower electrode bias frequency can range from about 0.1MHz to about 100 MHz, e.g., about 2 MHz or 13.56 MHz.

In one embodiment, the oxidation process, the first etching process, andthe second etching process are performed in the same plasma processingsystem. In an alternate embodiment, the oxidation process, the firstetching process, and the second etching process are performed inseparate plasma processing systems.

In another embodiment, the oxidation process, the first etching process,and the second etching process are repeated multiple cycles, e.g., twoor more cycles until the spacer material 250 is removed from thesubstrate region 202 on substrate 210 and the capping region 201 of thegate structure 200 to leave behind the spacer sidewall 280.

In yet another embodiment, an over-etch process may be performed.

In one example, Table 1 provides exemplary process conditions for aspacer etch process sequence. The spacer etch process sequence includes:(A) an oxidation process that utilizes an oxygen-containing plasmacontaining a O₂; (B) a first etching process that utilizes plasma formedof a process composition containing a CF₄ and Ar; and (C) a secondetching process that utilizes plasma formed of a process compositioncontaining a CH₃F, O₂, and Ar. The oxidation process, the first etchingprocess, and the second etching process are performed in a plasmaprocessing system, such as the system depicted in FIG. 11.

The plasma processing system depicted in FIG. 11 includes a surface waveplasma (SWP) source that comprises a slot antenna, such as a radial lineslot antenna (RLSA). Plasma formed using RLSA has many characteristicsincluding, but not limited to, a plasma with lower electron temperatureand ion energy compared to other plasma sources. For a given substratebias, the RLSA plasma will have a lower ion energy compared to aconventional radio frequency (RF) plasma. The inventors believe thatthis feature may be especially useful for achieving a low recess duringan over-etch step.

The inventors suspect that the ion energy incident on the substrate isdirectly correlated to the oxide layer thickness created as a result ofetching which in turn causes recess formation. In the spacer etchprocess sequence, low ion energy may be important for minimum recess.This feature may not be specific to the sequence described in Table 1,but it may be important for the over-etch step.

TABLE 1 UEL RF LEL RF p T (° C.) (LEL-C, CF₄ Ar O₂ CH₃F Time ProcessDescription (W) (W) (mTorr) LEL-E) CFR (sccm) (sccm) (sccm) (sccm) (sec)(A) Oxidation process 3000 0 20 30/30 70 0 0 350 0 60 (B) First etchingprocess 2000 220 20 30/30 5 50 1000 0 0 4 (C) Second etching 1800 25 10030/30 5 0 1000 16 20 20/30 process

For each etch process, a process condition is recited including an orderfor the etch steps in each etch process, an upper electrode (UEL) power(watts, W; e.g., microwave or RF power to upper electrode or antenna), alower electrode (LEL) power (watts, W), a gas pressure (millitorr,mtorr) in the plasma processing chamber, a temperature set forcomponents in the plasma processing chamber (° C.) (“LEL-C”=Lowerelectrode center temperature; “LEL-E”=Lower electrode edge temperature),a CF₄ flow rate (standard cubic centimeters per minute, sccm), an Arflow rate, an O₂ flow rate, a CH₃F flow rate, and time (sec, seconds).For the second etching process, the etch time was 20 sec for a bulksilicon substrate and 30 sec for a fully depleted silicon-on-insulator(SOI) substrate.

Table 2 provides results for performing the spacer etch process sequenceon a bulk silicon pFET (positive channel field effect transistor) and afully depleted SOI pFET. The spacer material included silicon nitrideand was deposited with an initial spacer material CD of 9 nm. Table 2provides the spacer etch requirement, as well as the actual data,including center (C)-edge (E) data, for both the FDSOI pFET and the bulkSi pFET. Using the spacer etch process sequence of Table 1, a sidewallspacer was produced having less than 1 nm spacer material CD reductionor slimming. The sidewall spacer exhibited no observable footing andsubstantially no recess at the substrate region of the substrate (e.g.,<1 nm). Furthermore, the spacer recess was less than 5% and theuniformity was less than 10% C/E. The gate capping layer, which includedSiO₂, had an initial capping layer thickness of about 15 nm and wasreduced to 11.6 nm in both cases.

TABLE 2 Spacer Etch Actual C/E Actual C/E Performance Metric RequirementFDSOI PFET BULK PFET Spacer material CD (final) >8 nm 8.2/8.7 nm 8.8/8.5nm Profile (footing) 0 nm 0/0 nm 0/0 nm Substrate recess (SiGe) <1 nm NA0/0 nm Substrate recess (Si) <1 nm 0/0 nm NA Spacer recess (SiN) <5 nm<5 nm <5 nm Uniformity 8% 9.70% 9.70%

One or more of the methods for performing a spacer etch process sequencedescribed above may be performed utilizing a plasma processing systemsuch as the one described in FIG. 11. However, the methods discussed arenot to be limited in scope by this exemplary presentation. The methodfor performing a spacer etch process sequence according to variousembodiments described above may be performed in any one of the plasmaprocessing systems illustrated in FIGS. 5 through 11 and describedbelow.

According to one embodiment, a plasma processing system 500 configuredto perform the above identified process conditions is depicted in FIG. 5comprising a plasma processing chamber 510, substrate holder 520, uponwhich a substrate 525 to be processed is affixed, and vacuum pumpingsystem 550. Substrate 525 can be a semiconductor substrate, a wafer, aflat panel display, or a liquid crystal display. Plasma processingchamber 510 can be configured to facilitate the generation of plasma inplasma processing region 545 in the vicinity of a surface of substrate525. An ionizable gas or mixture of process gases is introduced via agas distribution system 540. For a given flow of process gas, theprocess pressure is adjusted using the vacuum pumping system 550. Plasmacan be utilized to create materials specific to a pre-determinedmaterials process, and/or to aid the removal of material from theexposed surfaces of substrate 525. The plasma processing system 500 canbe configured to process substrates of any desired size, such as 200 mmsubstrates, 300 mm substrates, or larger.

Substrate 525 can be affixed to the substrate holder 520 via a clampingsystem 528, such as a mechanical clamping system or an electricalclamping system (e.g., an electrostatic clamping system). Furthermore,substrate holder 520 can include a heating system (not shown) or acooling system (not shown) that is configured to adjust and/or controlthe temperature of substrate holder 520 and substrate 525. The heatingsystem or cooling system may comprise a re-circulating flow of heattransfer fluid that receives heat from substrate holder 520 andtransfers heat to a heat exchanger system (not shown) when cooling, ortransfers heat from the heat exchanger system to substrate holder 520when heating. In other embodiments, heating/cooling elements, such asresistive heating elements, or thermo-electric heaters/coolers can beincluded in the substrate holder 520, as well as the chamber wall of theplasma processing chamber 510 and any other component within the plasmaprocessing system 500.

Additionally, a heat transfer gas can be delivered to the backside ofsubstrate 525 via a backside gas supply system 526 in order to improvethe gas-gap thermal conductance between substrate 525 and substrateholder 520. Such a system can be utilized when temperature control ofthe substrate is required at elevated or reduced temperatures. Forexample, the backside gas supply system can comprise a two-zone gasdistribution system, wherein the helium gas-gap pressure can beindependently varied between the center and the edge of substrate 525.

In the embodiment shown in FIG. 5, substrate holder 520 can comprise anelectrode 522 through which RF power is coupled to the processing plasmain plasma processing region 545. For example, substrate holder 520 canbe electrically biased at a RF voltage via the transmission of RF powerfrom a RF generator 530 through an optional impedance match network 532to substrate holder 520. The RF electrical bias can serve to heatelectrons to form and maintain plasma. In this configuration, the systemcan operate as a reactive ion etch (RIE) reactor, wherein the chamberand an upper gas injection electrode serve as ground surfaces. A typicalfrequency for the RF bias can range from about 0.1 MHz to about 100 MHz.RF systems for plasma processing are well known to those skilled in theart.

Furthermore, the electrical bias of electrode 522 at a RF voltage may bepulsed using pulsed bias signal controller 531. The RF power output fromthe RF generator 530 may be pulsed between an off-state and an on-state,for example.

Alternately, RF power is applied to the substrate holder electrode atmultiple frequencies. Furthermore, impedance match network 532 canimprove the transfer of RF power to plasma in plasma processing chamber510 by reducing the reflected power. Match network topologies (e.g.L-type, -type, T-type, etc.) and automatic control methods are wellknown to those skilled in the art.

Gas distribution system 540 may comprise a showerhead design forintroducing a mixture of process gases. Alternatively, gas distributionsystem 540 may comprise a multi-zone showerhead design for introducing amixture of process gases and adjusting the distribution of the mixtureof process gases above substrate 525. For example, the multi-zoneshowerhead design may be configured to adjust the process gas flow orcomposition to a substantially peripheral region above substrate 525relative to the amount of process gas flow or composition to asubstantially central region above substrate 525.

Vacuum pumping system 550 can include a turbo-molecular vacuum pump(TMP) capable of a pumping speed up to about 5000 liters per second (andgreater) and a gate valve for throttling the chamber pressure. Inconventional plasma processing devices utilized for dry plasma etching,a 1000 to 3000 liter per second TMP can be employed. TMPs are useful forlow pressure processing, typically less than about 50 mTorr. For highpressure processing (i.e., greater than about 100 mTorr), a mechanicalbooster pump and dry roughing pump can be used. Furthermore, a devicefor monitoring chamber pressure (not shown) can be coupled to the plasmaprocessing chamber 510.

Controller 555 comprises a microprocessor, memory, and a digital I/Oport capable of generating control voltages sufficient to communicateand activate inputs to plasma processing system 500 as well as monitoroutputs from plasma processing system 500. Moreover, controller 555 canbe coupled to and can exchange information with RF generator 530, pulsedbias signal controller 531, impedance match network 532, the gasdistribution system 540, vacuum pumping system 550, as well as thesubstrate heating/cooling system (not shown), the backside gas supplysystem 526, and/or the electrostatic clamping system 528. For example, aprogram stored in the memory can be utilized to activate the inputs tothe aforementioned components of plasma processing system 500 accordingto a process recipe in order to perform a plasma assisted process, suchas a plasma etch process, on substrate 525.

Controller 555 can be locally located relative to the plasma processingsystem 500, or it can be remotely located relative to the plasmaprocessing system 500. For example, controller 555 can exchange datawith plasma processing system 500 using a direct connection, anintranet, and/or the internet. Controller 555 can be coupled to anintranet at, for example, a customer site (i.e., a device maker, etc.),or it can be coupled to an intranet at, for example, a vendor site(i.e., an equipment manufacturer). Alternatively or additionally,controller 555 can be coupled to the internet. Furthermore, anothercomputer (i.e., controller, server, etc.) can access controller 555 toexchange data via a direct connection, an intranet, and/or the internet.

In the embodiment shown in FIG. 6, plasma processing system 600 can besimilar to the embodiment of FIG. 5 and further comprise either astationary, or mechanically or electrically rotating magnetic fieldsystem 660, in order to potentially increase plasma density and/orimprove plasma processing uniformity, in addition to those componentsdescribed with reference to FIG. 5. Moreover, controller 555 can becoupled to magnetic field system 660 in order to regulate the speed ofrotation and field strength. The design and implementation of a rotatingmagnetic field is well known to those skilled in the art.

In the embodiment shown in FIG. 7, plasma processing system 700 can besimilar to the embodiment of FIG. 5 or FIG. 6, and can further comprisean upper electrode 770 to which RF power can be coupled from RFgenerator 772 through optional impedance match network 774. A frequencyfor the application of RF power to the upper electrode can range fromabout 0.1 MHz to about 200 MHz. Additionally, a frequency for theapplication of power to the lower electrode can range from about 0.1 MHzto about 100 MHz. Moreover, controller 555 is coupled to RF generator772 and impedance match network 774 in order to control the applicationof RF power to upper electrode 770. The design and implementation of anupper electrode is well known to those skilled in the art. The upperelectrode 770 and the gas distribution system 540 can be designed withinthe same chamber assembly, as shown. Alternatively, upper electrode 770may comprise a multi-zone electrode design for adjusting the RF powerdistribution coupled to plasma above substrate 525. For example, theupper electrode 770 may be segmented into a center electrode and an edgeelectrode.

In the embodiment shown in FIG. 8, plasma processing system 800 can besimilar to the embodiment of FIG. 7, and can further comprise a directcurrent (DC) power supply 890 coupled to the upper electrode 770opposing substrate 525. The upper electrode 770 may comprise anelectrode plate. The electrode plate may comprise a silicon-containingelectrode plate. Moreover, the electrode plate may comprise a dopedsilicon electrode plate. The DC power supply 890 can include a variableDC power supply. Additionally, the DC power supply 890 can include abipolar DC power supply. The DC power supply 890 can further include asystem configured to perform at least one of monitoring, adjusting, orcontrolling the polarity, current, voltage, or on/off state of the DCpower supply 890. Once plasma is formed, the DC power supply 890facilitates the formation of a ballistic electron beam. An electricalfilter (not shown) may be utilized to de-couple RF power from the DCpower supply 890.

For example, the DC voltage applied to upper electrode 770 by DC powersupply 890 may range from approximately −2000 volts (V) to approximately1000 V. Desirably, the absolute value of the DC voltage has a valueequal to or greater than approximately 100 V, and more desirably, theabsolute value of the DC voltage has a value equal to or greater thanapproximately 500 V. Additionally, it is desirable that the DC voltagehas a negative polarity. Furthermore, it is desirable that the DCvoltage is a negative voltage having an absolute value greater than theself-bias voltage generated on a surface of the upper electrode 770. Thesurface of the upper electrode 770 facing the substrate holder 520 maybe comprised of a silicon-containing material.

In the embodiment shown in FIG. 9, plasma processing system 900 can besimilar to the embodiments of FIGS. 5 and 6, and can further comprise aninductive coil 980 to which RF power is coupled via RF generator 982through optional impedance match network 984. RF power is inductivelycoupled from inductive coil 980 through a dielectric window (not shown)to plasma processing region 545. A frequency for the application of RFpower to the inductive coil 980 can range from about 10 MHz to about 100MHz. Similarly, a frequency for the application of power to the chuckelectrode can range from about 0.1 MHz to about 100 MHz. In addition, aslotted Faraday shield (not shown) can be employed to reduce capacitivecoupling between the inductive coil 980 and plasma in the plasmaprocessing region 545. Moreover, controller 555 can be coupled to RFgenerator 982 and impedance match network 984 in order to control theapplication of power to inductive coil 980.

In an alternate embodiment, as shown in FIG. 10, plasma processingsystem 1000 can be similar to the embodiment of FIG. 9, and can furthercomprise an inductive coil 1080 that is a “spiral” coil or “pancake”coil in communication with the plasma processing region 545 from aboveas in a transformer coupled plasma (TCP) reactor. The design andimplementation of an inductively coupled plasma (ICP) source, ortransformer coupled plasma (TCP) source, is well known to those skilledin the art.

Alternately, plasma can be formed using electron cyclotron resonance(ECR). In yet another embodiment, the plasma is formed from thelaunching of a Helicon wave. In yet another embodiment, the plasma isformed from a propagating surface wave. Each plasma source describedabove is well known to those skilled in the art.

In the embodiment shown in FIG. 11, plasma processing system 1100 can besimilar to the embodiment of FIG. 5, and can further comprise a surfacewave plasma (SWP) source 1130. The SWP source 1130 can comprise a slotantenna, such as a radial line slot antenna (RLSA), to which microwavepower is coupled via a power coupling system 1190.

Referring now to FIG. 12, a schematic representation of a SWP source1230 is provided according to an embodiment. The SWP source 1230comprises an electromagnetic (EM) wave launcher 1232 configured tocouple EM energy in a desired EM wave mode to a plasma by generating asurface wave on a plasma surface 1260 of the EM wave launcher 1232adjacent plasma. Furthermore, the SWP source 1230 comprises a powercoupling system 1290 coupled to the EM wave launcher 1232, andconfigured to provide the EM energy to the EM wave launcher 1232 forforming the plasma.

The EM wave launcher 1232 includes a microwave launcher configured toradiate microwave power into plasma processing region 545 (see FIG. 11).The EM wave launcher 1232 is coupled to the power coupling system 1290via coaxial feed 1238 through which microwave energy is transferred. Thepower coupling system 1290 includes a microwave source 1292, such as a2.45 GHz microwave power source. Microwave energy generated by themicrowave source 1292 is guided through a waveguide 1294 to an isolator1296 for absorbing microwave energy reflected back to the microwavesource 1292. Thereafter, the microwave energy is converted to a coaxialTEM (transverse electromagnetic) mode via a coaxial converter 1298.

A tuner may be employed for impedance matching, and improved powertransfer. The microwave energy is coupled to the EM wave launcher 1232via the coaxial feed 1238, wherein another mode change occurs from theTEM mode in the coaxial feed 1238 to a TM (transverse magnetic) mode.Additional details regarding the design of the coaxial feed 1238 and theEM wave launcher 1232 can be found in U.S. Pat. No. 5,024,716, entitled“Plasma processing apparatus for etching, ashing, and film-formation”;the content of which is herein incorporated by reference in itsentirety.

Referring now to FIGS. 13A and 13B, a schematic cross-sectional view anda bottom view, respectively, of an EM wave launcher 1332 are providedaccording to one embodiment. The EM wave launcher 1332 comprises acoaxial feed 1338 having an inner conductor 1340, an outer conductor1342, and insulator 1341, such as an air gap, and a slot antenna 1346having a plurality of slots 1348 coupled between the inner conductor1340 and the outer conductor 1342 as shown in FIG. 13A. The plurality ofslots 1348 permits the coupling of EM energy from a first region abovethe slot antenna 1346 to a second region below the slot antenna 1346,wherein plasma is formed adjacent a plasma surface 1360 on the EM wavelauncher 1332. The EM wave launcher 1332 may further comprise a slowwave plate 1344, and a resonator plate 1350.

The number, geometry, size, and distribution of the slots 1348 are allfactors that can contribute to the spatial uniformity of the plasmaformed in the plasma processing region 545 (see FIG. 11). Thus, thedesign of the slot antenna 1346 may be used to control the spatialuniformity of the plasma in the plasma processing region 545 (see FIG.11).

As shown in FIG. 13A, the EM wave launcher 1332 may comprise a fluidchannel 1356 that is configured to flow a temperature control fluid fortemperature control of the EM wave launcher 1332. Although not shown,the EM wave launcher 1332 may further be configured to introduce aprocess gas through the plasma surface 1360 to the plasma. Although notshown, a gas distribution system, such as the gas distribution system(540) of FIG. 11, may be connected to the EM wave launcher 1332 and/orthe chamber wall 1352 for introducing a process gas into the processchamber.

Referring still to FIG. 13A, the EM wave launcher 1332 may be coupled toan upper chamber portion of a plasma processing system, wherein a vacuumseal can be formed between an upper chamber wall 1352 and the EM wavelauncher 1332 using a sealing device 1354. The sealing device 1354 caninclude an elastomer O-ring; however, other known sealing mechanisms maybe used.

In general, the inner conductor 1340 and the outer conductor 1342 of thecoaxial feed 1338 comprise a conductive material, such as a metal, whilethe slow wave plate 1344 and the resonator plate 1350 comprise adielectric material. In the latter, the slow wave plate 1344 and theresonator plate 1350 preferably comprise the same material; however,different materials may be used. The material selected for fabricationof the slow wave plate 1344 is chosen to reduce the wavelength of thepropagating electromagnetic (EM) wave relative to the correspondingfree-space wavelength, and the dimensions of the slow wave plate 1344and the resonator plate 1350 are chosen to ensure the formation of astanding wave effective for radiating EM energy into the plasmaprocessing region 545 (see FIG. 11).

The slow wave plate 1344 and the resonator plate 1350 can be fabricatedfrom a dielectric material, including silicon-containing materials suchas quartz (silicon dioxide), or a high dielectric constant (high-k)materials. For example, the high-k material may possess a dielectricconstant greater than a value of 4. In particular, when the plasmaprocessing system is utilized for etch process applications, quartz isoften chosen for compatibility with the etch process.

For example, the high-k material can include intrinsic crystal silicon,alumina ceramic, aluminum nitride, and sapphire. However, other high-kmaterials may be used. Moreover, a particular high-k material may beselected in accordance with the parameters of a particular process. Forexample, when the resonator plate 1350 is fabricated from intrinsiccrystal silicon, the plasma frequency exceeds 2.45 GHz at a temperatureof 45 degrees C. Therefore, intrinsic crystal silicon is appropriate forlow temperature processes (i.e., less than 45 degrees C.). For highertemperature processes, the resonator plate 1350 can be fabricated fromalumina (Al₂O₃), or sapphire.

Plasma uniformity and plasma stability may remain as challenges for thepractical implementation of a SWP source as described above. In thelatter, the standing wave at the resonator plate-plasma interface, i.e.,at the plasma surface 1360, may be prone to mode jumps as plasmaparameters shift.

As shown in FIGS. 13A and 13B, the EM wave launcher 1332 may befabricated with a first recess configuration 1362 formed in the plasmasurface 1360 and optionally a second recess configuration 1364 formed inthe plasma surface 1360 according to one embodiment.

The first recess configuration 1362 may comprise a first plurality ofrecesses. Each recess in the first recess configuration 1362 maycomprise a unique indentation or dimple formed within the plasma surface1360. For example, a recess in the first recess configuration 1362 maycomprise a cylindrical geometry, a conical geometry, a frusto-conicalgeometry, a spherical geometry, an aspherical geometry, a rectangulargeometry, a pyramidal geometry, or any arbitrary shape. The first recessdistribution 1362 may comprise recesses characterized by a first size(e.g., latitudinal dimension (or width), and/or longitudinal dimension(or depth)).

The second recess configuration 1364 may comprise a plurality ofrecesses. Each recess in the second recess configuration 1364 maycomprise a unique indentation or dimple formed within the plasma surface1360. For example, a recess in the second recess configuration 1364 maycomprise a cylindrical geometry, a conical geometry, a frusto-conicalgeometry, a spherical geometry, an aspherical geometry, a rectangulargeometry, a pyramidal geometry, or any arbitrary shape. The secondrecess distribution 1364 may comprise recesses characterized by a secondsize (e.g., latitudinal dimension (or width), and/or longitudinaldimension (or depth)). The first size of the recesses in the firstrecess configuration 1362 may or may not be the same as the second sizeof the recesses in the second recess configuration 1364. For instance,the second size may be smaller than the first size.

As shown in FIGS. 13A and 13B, the resonator plate 1350 comprises adielectric plate having a plate diameter and a plate thickness. Therein,the plasma surface 1360 on resonator plate 1350 comprises a planarsurface 1366 within which the first recess configuration 1362 and thesecond recess configuration 1364 are formed. Alternatively, theresonator plate 1350 comprises a non-planar geometry or an arbitrarygeometry. Therein, the plasma surface 1360 may comprise a non-planarsurface within which the first recess configuration and the secondrecess configuration are formed (not shown). For example, the non-planarsurface may be concave, or convex, or a combination thereof.

The propagation of EM energy in the resonator plate 1350 may becharacterized by an effective wavelength ( ) for a given frequency of EMenergy and dielectric constant for the resonator plate 1350. The platethickness may be an integer number of quarter wavelengths (n/4, where nis an integer greater than zero) or an integer number of halfwavelengths (m/2, where m is an integer greater than zero). Forinstance, the plate thickness may be about half the effective wavelength(/2) or greater than half the effective wavelength (>/2). Alternatively,the plate thickness may be a non-integral fraction of the effectivewavelength (i.e., not an integral number of half or quarterwavelengths). Alternatively yet, the plate thickness may range fromabout 25 mm (millimeters) to about 45 mm.

As an example, the first recess configuration 1362 may comprise a firstplurality of cylindrical recesses, wherein each of the first pluralityof cylindrical recesses is characterized by a first depth and a firstdiameter. As shown in FIG. 13B, the first recess configuration 1362 islocated near an outer region of the plasma surface 1360.

The first diameter may be an integer number of quarter wavelengths (n/4,where n is an integer greater than zero), or an integer number of halfwavelengths (m/2, where m is an integer greater than zero), or anon-integral fraction of the effective wavelength. Additionally, a firstdifference between the plate thickness and the first depth may be aninteger number of quarter wavelengths (n/4, where n is an integergreater than zero), or an integer number of half wavelengths (m/2, wherem is an integer greater than zero), or a non-integral fraction of theeffective wavelength. For instance, the first diameter may be about halfthe effective wavelength (/2), and the first difference between theplate thickness and the first depth may be about half the effectivewavelength (/2) or about quarter the effective wavelength (/4).Additionally, for instance, the plate thickness may be about half theeffective wavelength (/2) or greater than half the effective wavelength(>/2).

Alternatively, the first diameter may range from about 25 mm to about 35mm, and the first difference between the plate thickness and the firstdepth may range from about 10 mm to about 35 mm. Alternatively yet, thefirst diameter may range from about 30 mm to about 35 mm, and the firstdifference may range from about 10 mm to about 20 mm. Alternatively yet,the first diameter and/or first depth may be a fraction of the platethickness.

In the first recess configuration 1362, chamfers, rounds and/or fillets(i.e., surface/corner radius or bevel) may be utilized to affect smoothsurface transitions between adjacent surfaces. In a cylindrical recess,a surface radius may be disposed at the corner between the cylindricalsidewall and the bottom of the recess. Additionally, in a cylindricalrecess, a surface radius may be disposed at the corner between thecylindrical sidewall and the plasma surface 1360. For example, thesurface radius may range from about 1 mm to about 3 mm.

As another example, the second recess configuration 1364 may comprise asecond plurality of cylindrical recesses, each of the second pluralityof cylindrical recesses being characterized by a second depth and asecond diameter. As shown in FIG. 13B, the second recess configuration1364 is located near an inner region of the plasma surface 1360.

The second diameter may be an integer number of quarter wavelengths(n/4, where n is an integer greater than zero), or an integer number ofhalf wavelengths (m/2, where m is an integer greater than zero), or anon-integral fraction of the effective wavelength. Additionally, asecond difference between the plate thickness and the second depth maybe an integer number of quarter wavelengths (n/4, where n is an integergreater than zero), or an integer number of half wavelengths (m/2, wherem is an integer greater than zero), or a non-integral fraction of theeffective wavelength. For instance, the second diameter may be abouthalf the effective wavelength (/2), and the second difference betweenthe plate thickness and the second depth may be about half the effectivewavelength (/2) or about quarter the effective wavelength (/4).Additionally, for instance, the plate thickness may be about half theeffective wavelength (/2) or greater than half the effective wavelength(>/2).

Alternatively, the second diameter may range from about 25 mm to about35 mm, and the second difference between the plate thickness and thesecond depth may range from about 10 mm to about 35 mm. Alternativelyyet, the second diameter may range from about 30 mm to about 35 mm, andthe second difference may range from about 10 mm to about 20 mm.Alternatively yet, the second diameter and/or second depth may be afraction of the plate thickness.

In the second recess configuration 1364, chamfers, rounds and/or fillets(i.e., surface/corner radius or bevel) may be utilized to affect smoothsurface transitions between adjacent surfaces. In a cylindrical recess,a surface radius may be disposed at the corner between the cylindricalsidewall and the bottom of the recess. Additionally, in a cylindricalrecess, a surface radius may be disposed at the corner between thecylindrical sidewall and the plasma surface 1360. For example, thesurface radius may range from about 1 mm to about 3 mm.

Referring again to FIG. 13B, a bottom view of the EM wave launcher 1332depicted in FIG. 13A is provided. The plurality of slots 1348 in slotantenna 1346 are illustrated as if one can see through resonator plate1350 to the slot antenna 1346. As shown in FIG. 13B, the plurality ofslots 1348 may be arranged in pairs, wherein each of the pair of slotscomprises a first slot oriented orthogonal to a second slot. However,the orientation of slots in the plurality of slots 1348 may bearbitrary. For example, the orientation of slots in the plurality ofslots 1348 may be according to a pre-determined pattern for plasmauniformity and/or plasma stability.

The first recess configuration 1362 is substantially aligned with afirst arrangement of slots in the plurality of slots 1348. Therein, atleast one recess of the first recess configuration 1362 may be aligned,partially aligned, or not aligned with one or more of the plurality ofslots 1348. The second recess configuration 1364 is either partlyaligned with a second arrangement of slots in the plurality of slots1348 or not aligned with the second arrangement of slots in theplurality of slots 1348. As shown in FIG. 13B, the second recessconfiguration 1364 is not aligned with the second arrangement of slotsin the plurality of slots 1348.

As a consequence, the arrangement of the first and second recessconfigurations 1362, 1364 and their alignment with one or more of theplurality of slots 1348 may be optimized to control and/or improveplasma uniformity and/or stability. Additional details regarding thedesign of the plasma surface 1360 and the EM wave launcher 1332 can befound in pending U.S. Patent Application Publication Serial No.2011/0057562, entitled “Stable surface wave plasma source”, and filed onSep. 8, 2009; the content of which is herein incorporated by referencein its entirety.

Referring now to FIG. 14, a schematic cross-sectional view of an EM wavelauncher 1432 is provided according to another embodiment. The EM wavelauncher 1432 comprises the coaxial feed 1438 having an inner conductor1440, an outer conductor 1442, and insulator 1441, such as an air gap,and a slot antenna 1446 having a plurality of slots 1448 coupled betweenthe inner conductor 1440 and the outer conductor 1442 as shown in FIG.14. The plurality of slots 1448 permits the coupling of EM energy from afirst region above the slot antenna 1446 to a second region below theslot antenna 1446, wherein plasma is formed adjacent a plasma surface1460 on the EM wave launcher 1432. The EM wave launcher 1432 may furthercomprise a slow wave plate 1444, and a resonator plate 1450.

The number, geometry, size, and distribution of the slots 1448 are allfactors that can contribute to the spatial uniformity of the plasmaformed in the plasma processing region 545 (see FIG. 11). Thus, thedesign of the slot antenna 1446 may be used to control the spatialuniformity of the plasma in the plasma processing region 545 (see FIG.11).

As shown in FIG. 14, the EM wave launcher 1432 may comprise a fluidchannel 1456 that is configured to flow a temperature control fluid fortemperature control of the EM wave launcher 1432. Although not shown, agas distribution system, such as the gas distribution system (540) ofFIG. 11, may be connected to the EM wave launcher 1432 and/or thechamber wall 1452 for introducing a process gas into the processchamber.

Referring still to FIG. 14, the EM wave launcher 1432 may be coupled toan upper chamber portion of a plasma processing system, wherein a vacuumseal can be formed between an upper chamber wall 1452 and the EM wavelauncher 1432 using a sealing device 1454. The sealing device 1454 caninclude an elastomer O-ring; however, other known sealing mechanisms maybe used.

In general, the inner conductor 1440 and the outer conductor 1442 of thecoaxial feed 1438 comprise a conductive material, such as a metal, whilethe slow wave plate 1444 and the resonator plate 1450 comprise adielectric material. In the latter, the slow wave plate 1444 and theresonator plate 1450 preferably comprise the same material; however,different materials may be used. The material selected for fabricationof the slow wave plate 1444 is chosen to reduce the wavelength of thepropagating electromagnetic (EM) wave relative to the correspondingfree-space wavelength, and the dimensions of the slow wave plate 1444and the resonator plate 1450 are chosen to ensure the formation of astanding wave effective for radiating EM energy into the plasmaprocessing region 545 (see FIG. 11).

The slow wave plate 1444 and the resonator plate 1450 can be fabricatedfrom a dielectric material, including silicon-containing materials suchas quartz (silicon dioxide), or a high dielectric constant (high-k)materials. For example, the high-k material may possess a dielectricconstant greater than a value of 4. In particular, when the plasmaprocessing system is utilized for etch process applications, quartz isoften chosen for compatibility with the etch process.

For example, the high-k material can include intrinsic crystal silicon,alumina ceramic, aluminum nitride, and sapphire. However, other high-kmaterials may be used. Moreover, a particular high-k material may beselected in accordance with the parameters of a particular process. Forexample, when the resonator plate 1450 is fabricated from intrinsiccrystal silicon, the plasma frequency exceeds 2.45 GHz at a temperatureof 45 degrees C. Therefore, intrinsic crystal silicon is appropriate forlow temperature processes (i.e., less than 45 degrees C.). For highertemperature processes, the resonator plate 1450 can be fabricated fromalumina (Al₂O₃), or sapphire.

Plasma uniformity and plasma stability may remain as challenges for thepractical implementation of a SWP source as described above. In thelatter, the standing wave at the resonator plate-plasma interface, i.e.,at the plasma surface 1460, may be prone to mode jumps as plasmaparameters shift.

As shown in FIG. 14, the EM wave launcher 1432 may be fabricated with afirst recess configuration 1462 formed in the plasma surface 1460 andoptionally a second recess configuration 1464 formed in the plasmasurface 1460 according to one embodiment.

The first recess configuration 1462 may comprise a first channel recess.For example, the first channel recess in the first recess configuration1462 may include a cross-section that has a frusto-conical geometry.However, other geometries may be used, e.g., a spherical geometry, anaspherical geometry, a rectangular geometry, a pyramidal geometry, orany arbitrary shape. The first recess distribution 1462 may comprise achannel recess characterized by a first size (e.g., latitudinaldimension (or width), and/or longitudinal dimension (or depth)).

The second recess configuration 1464 may comprise a second channelrecess. For example, the second channel recess in the second recessconfiguration 1464 may include a cross-section that has a frusto-conicalgeometry. However, other geometries may be used, e.g., a sphericalgeometry, an aspherical geometry, a rectangular geometry, a pyramidalgeometry, or any arbitrary shape. The second recess distribution 1464may comprise a channel recess characterized by a second size (e.g.,latitudinal dimension (or width), and/or longitudinal dimension (ordepth)). The first size of the first channel recess in the first recessconfiguration 1462 may or may not be the same as the second size of thesecond channel recess in the second recess configuration 1464. Forinstance, the second size may be larger than the first size.

As shown in FIG. 14, the resonator plate 1450 comprises a dielectricplate having a plate diameter and a plate thickness. Therein, the plasmasurface 1460 on resonator plate 1450 comprises a planar surface 1466within which the first recess configuration 1462 and the second recessconfiguration 1464 are formed. Alternatively, the resonator plate 1450comprises a non-planar geometry or an arbitrary geometry. Therein, theplasma surface 1460 may comprise a non-planar surface within which thefirst recess configuration and the second recess configuration areformed (not shown). For example, the non-planar surface may be concave,or convex, or a combination thereof.

The arrangement of the first and second recess configurations (1462,1464) and their alignment with one or more of the plurality of slots1448 may be optimized to control and/or improve plasma uniformity and/orstability. Additional details regarding the design of the plasma surface1460 and the EM wave launcher 1432 can be found in pending U.S. patentapplication Ser. No. 10/570,631, entitled “Plasma processing equipment”,filed on Dec. 19, 2006, and published as U.S. Patent ApplicationPublication No. 2007/0113788A1; the content of which is hereinincorporated by reference in its entirety.

Although only certain embodiments of this invention have been describedin detail above, those skilled in the art will readily appreciate thatmany modifications are possible in the embodiments without materiallydeparting from the novel teachings and advantages of this invention.Accordingly, all such modifications are intended to be included withinthe scope of this invention.

What is claimed is:
 1. A method for performing a spacer etch,comprising: providing a substrate having a spacer material conformallyapplied over a gate structure; exposing an exposed surface of saidspacer material to an oxygen-containing environment to elevate an oxygencontent in said spacer material; and performing a spacer etch processsequence to partially and selectively remove said spacer material from acapping region of said gate structure and a substrate region on saidsubstrate adjacent a base of said gate structure, while retaining aspacer sidewall positioned along a sidewall of said gate structure. 2.The method of claim 1, wherein said spacer material comprises siliconnitride, silicon carbide, or silicon carbonitride.
 3. The method ofclaim 2, wherein said spacer material conformally applied over said gatestructure has a thickness less than or equal to about 10 nanometers(nm).
 4. The method of claim 1, wherein said oxygen-containingenvironment contains an oxygen-containing plasma.
 5. The method of claim4, wherein said oxygen-containing environment contains O, O₂, O₃, CO,CO₂, NO, N₂O, or NO₂, or any combination of two or more thereof.
 6. Themethod of claim 1 wherein performing said spacer etch process sequencecomprises: performing a first etching process to anisotropically removesaid spacer oxidation layer from said spacer material at said substrateregion on said substrate and said spacer material at said capping regionof said gate structure, while substantially retaining said spaceroxidation layer on said spacer material along said sidewall of said gatestructure, and performing a second etching process to selectively removesaid spacer material from said substrate region on said substrate andsaid capping region of said gate structure to leave behind said spacersidewall on said sidewall of said gate structure.
 7. The method of claim6, wherein said performing said first etching process comprises formingplasma from a first etching process composition containing a halomethanegas and a noble gas.
 8. The method of claim 7, wherein said performingsaid first etching process comprises: introducing said first etchingprocess composition containing CF₄ and Ar to a plasma processing system,setting a pressure in said plasma processing system at or less thanabout 50 mTorr, forming a first etching plasma from said first etchingprocess composition, and exposing said substrate to said first etchingplasma.
 9. The method of claim 8, wherein said performing said firstetching process further comprises: forming said first etching plasma bycoupling electromagnetic (EM) radiation from a radial line slot antennato said first etching process composition, and applying an electricalbias to said substrate by coupling radio frequency (RF) power to asubstrate holder upon which said substrate rests.
 10. The method ofclaim 9, wherein said forming said first etching plasma comprisescoupling electromagnetic (EM) energy at a microwave frequency in adesired EM wave mode to said first etching plasma by generating asurface wave on a plasma surface of an EM wave launcher adjacent saidfirst etching plasma, said EM wave launcher comprises a slot antennahaving a plurality of slots formed there through configured to couplesaid EM energy from a first region above said slot antenna to a secondregion below said slot antenna.
 11. The method of claim 6, wherein saidperforming said second etching process comprises forming plasma from asecond etching process composition containing a halomethane gas, anoxygen-containing gas, and a noble gas.
 12. The method of claim 11,wherein said performing said second etching process comprises:introducing said second etching process composition containing CH₃F, O₂,and Ar to a plasma processing system, setting a pressure in said plasmaprocessing system at or greater than about 50 mTorr, forming a secondetching plasma from said second etching process composition, andexposing said substrate to said second etching plasma.
 13. The method ofclaim 12, wherein said performing said second etching process furthercomprises: forming said second etching plasma by coupling EM radiationfrom a radial line slot antenna (RLSA) to said second etching processcomposition, and applying an electrical bias to said substrate bycoupling RF power to a substrate holder upon which said substrate rests.14. The method of claim 13, wherein said forming said second etchingplasma comprises coupling electromagnetic (EM) energy at a microwavefrequency in a desired EM wave mode to said second etching plasma bygenerating a surface wave on a plasma surface of an EM wave launcheradjacent said first etching plasma, said EM wave launcher comprises aslot antenna having a plurality of slots formed there through configuredto couple said EM energy from a first region above said slot antenna toa second region below said slot antenna.
 15. The method of claim 1,further comprising: selecting process conditions for said spacer etchprocess sequence to achieve a substrate recess at said substrate regionon said substrate adjacent said base of said gate structure having avalue of 1.5 nm or less.
 16. The method of claim 1, further comprising:selecting process conditions for said spacer etch process sequence toachieve a substrate recess at said substrate region on said substrateadjacent said base of said gate structure having a value of 1 nm orless.
 17. The method of claim 1, further comprising: selecting processconditions for said spacer etch process sequence to achieve a top recessat said top of said sidewall space on said gate structure having a valueof 5 nm or less; and/or selecting process conditions for said spaceretch process sequence to achieve a CD reduction of said sidewall spacerhaving a value of 2 nm or less; and/or selecting process conditions forsaid spacer etch process sequence to achieve substantially no footing atsaid base of said gate structure.
 18. The method of claim 1, wherein theexposing said exposed surface of said spacer material to anoxygen-containing environment and performing said spacer etch processsequence is performed more than once.
 19. The method of claim 12,wherein the plasma processing system comprises one of an electrodethrough which radio frequency (RF) power is coupled to the plasma, astationary or an upper electrode through which power can be coupled byan impedance generator, an upper electrode through which power can becoupled to an impedance generator with the upper electrode coupled to adirect current (DC) supply, an inductive coil to which RF power iscoupled via an RF generator through an optional impedance network, or anelectrode through which RF power and a surface wave plasma (SWP) sourceare coupled to the plasma.
 20. The method of claim 1, wherein the spacermaterial is applied over the gate structure using a chemical vapordeposition (CVD), a plasma enhanced chemical vapor deposition (PECVD),an atomic layer deposition (ALD), a plasma enhanced atomic layerdeposition (PEALD), or a physical vapor deposition (PVD) process; and/orthe oxygen-generating environment is an in situ or an ex situenvironment.